The present invention relates to a circuit for generating a delta value for use in a delta modulation system.
Generally, a delta modulation system has been used for digitally processing analog signals such as voice signals. A modulator (encoder) is comprised of a comparator, a local decoder and sample/hold circuit. An input analog signal and an estimated signal produced from the local decoder are supplied to the comparator and an output signal from the comparator is sampled and held to provide a coded signal. Since the coded signal is also applied to the local decoder functioning as an integrator, the estimate signal is incremented or decremented by a given minute value (a delta value) in accordance with a level of the coded signal and follows a change of the input signal, while changing stepwisely. In other words, the delta modulation means an encoding of one bit, with simple construction. The demodulator (decoder) is comprised of an integrator, as described above.
As described above, in the digital processing by making use of the delta modulation, the delta value is constant and therefore a pulse signal is produced even if no input voice is supplied. The pulse signal thus produced becomes a noise. This noise is called a granular noise. Also at the time of encoding, when the input analog signal rapidly changes, the estimated signal can not follow the rapid change of the input analog signal, producing an overload noise between the estimate signal and the input signal. These noises, in processing the voice signal, are reproduced giving noisy sound, so that an articulation of the reproduced voice is deteriorated. This problem is serious.
In general, the granular noise is smaller as the delta value is smaller, and the overload noise is smaller as the delta value is larger. To comply with the nature of those noises, an adaptive delta modulation system has recently been proposed, in which the delta value is not fixed but is changed in accordance with a change of the input signal. In order to reduce the overload noise, when the input signal is small, the delta value must be made small, while when the input signal change is large, the delta value must be made large. This is realized in a manner that, in a train of bits of the coded signal (the output signal for the encoding and the input signal for the decoding), when the same codes continuously appear in succession, the delta value is increased by a given value (several percentiles of the delta value), while when different codes appear in succession, it is decreased.
An example of a circuit for generating a delta value used in a conventional adaptive delta modulator is illustrated in FIG. 1. Assume that the delta value is expressed by a binary number of twelve bits, and that the circuit includes a register 10 comprised of twelve D flip-flops and an adder/subtractor 12 comprised of twelve full-adders. Output terminals Q of the flip-flops are connected to first input terminals A of corresponding adders, and connected to an integrator (not shown). Inverted output terminals Q of the upper 6 bits of those flip-flops in the register 10 are connected to second input terminals B of the adders of the lower six bits of adder/subtractor 12, respectively. A control terminal EXD at which level is set at logic 1 or 0 in accordance with a changing direction of the delta value is connected to second input terminals B of the adders of the upper six bits in the adder/substractor 12. A carry output terminal CA of the adder of each bit is connected to a carry input terminal C of the adder of the subsequent upper bit. The control terminal EXD is connected to a carry input terminal CA of the adder of the least significant bit. An output terminal S of each adder in the adder/subtractor 12 is connected to an input terminal D of the corresponding flip-flop in the register 10. A clock terminal 14 is connected to clock terminals CK of all the flip-flops in the register 10.
The operation of the conventional circuit will be described. The control terminal EXD is set at logic 0 when the same codes continue in the code bit train, while it is set to logic 1 when the same codes are not continued. A case where the control terminal EXD is set at logic 1 level will first be given. Assume that the delta value stored in the register 10, i.e. logic levels of the Q output data of the flip-flops, are d1, d2, . . . , d12 in the order from the least significant bit and that logic levels of the Q output data of the upper six bits are d7, d8, . . . , d12 in the order from the lower to higher bits. The adder/substractor 12 adds the A input data d1, d2, . . . , d4, d5, d6, . . . , d12 to the B input data d7, d8, . . . , d12, 1, 1, . . . , 1. When the present delta value is N(n) (in this case, N(n)=0 to 4095), the next delta value N(n+1) obtained by the arithmetic operation is given as follows: ##EQU1## Hence, an amount of change of the delta value is expressed as follows: ##EQU2##
A case where the control terminal EXD is set at logic 0 will be described. In this case, the B input data of the adders of the upper six bits are all logic 0. This leads to the following relation. ##EQU3## From the above equation, we have the following amount of change of the delta value. ##EQU4##
The amount of change of the delta value in the equation (2) is negative, and this indicates an amount of decrease. The amount of change of the delta value in the equation (4) is positive in the range of N(n) from 0 to 4095, and this indicates amount of increase. The amount of decrease (given by the equation (2)) with respect to the present delta value N(n) and the amount of increase (given by the equation (4)) with respect to the present delta value N(n) are respectively shown by a solid line and a broken line in FIG. 2. As given by the equations (2) and (4), as the delta value N(n) is larger, the amount of increase is smaller but the amount of decrease is large. Conversely, as the delta value is smaller, the amount of decrease is small but the amount of increase is larger. Accordingly, the delta value is prevented from being minimized or maximized.
Thus, in this circuit, the delta value may be increased or decreased in accordance with a signal at the control terminal EXD. As described above, the delta value is not maximized or minimized and a rate of increase of the delta value is equal to a rate of decrease. As a result, the delta value changes from the half of the maximum, 2047.5. The variation center value of the delta value means the delta value where the amount of increase is equal to the amount of decrease.
However, in the circuit, the variation center of the delta value is fixed, so that there is a case that an improper delta value is determined when the input signal has some characteristic. In the adaptive delta modulation system for processing the voice signal, a voice signal as the input signal has a variety of voice qualities since persons giving voices have such. The determination of the improper delta value is a very serious problem.
The adaptive delta modulator needs a delta value generating circuit, so that the construction is complicated and a large number of elements are used. In fabricating the circuit by the integrated circuit technology, this hinders an integration density from being made high.